1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor manufacturing method. More particularly, the present invention relates to a semiconductor device and a semiconductor manufacturing method, which can minimize a drop in a current gain at a time of an increase in a collector current density and also improve a variation in a collector current.
2. Description of the Related Art
As a conventional technique, for example, there is a technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 7-147287). That is, this is a SiGe base bipolar transistor, in which each of a base layer and a collector layer are constituted by a single crystal silicon layer containing germanium (Element Symbol: Ge), and an occurrence of a parasitic energy barrier is protected in a base-collector junction region, and a drop in a cut-off frequency is suppressed.
FIG. 1 is a device section view describing a conventional SiGe base bipolar transistor. In FIG. 1, a symbol 201 denotes a P-type silicon substrate. A symbol 202 denotes an N+-type buried layer. A symbol 203A denotes a first collector layer. A symbol 203B denotes a second collector layer. A symbol 205 denotes an insulation separation oxide film. A symbol 206 denotes a diffusion layer to pull out a collector. A symbol 207 denotes an oxide film. A symbol 208 denotes a P-type poly-crystal silicon layer to pull out an outer base. A symbol 209 denotes a silicon nitride film. A symbol 210 denotes a P-type SiGe base layer (silicon germanium base layer). A symbol 211 denotes a silicon nitride film. A symbol 212 denotes a poly-crystal silicon film to pull out an emitter. And, a symbol 213 denotes an emitter layer.
In the conventional SiGe base bipolar transistor, the N+-type buried layer 202 having a high concentration and the first collector layer 203A having a first Ge concentration distribution and the second collector layer 203B having a second Ge concentration distribution are formed on the P-type silicon substrate 201, as shown in FIG. 1. The P-type SiGe base layer 210 resulting from a selectively epitaxial growth and the emitter layer 213 constituted by an N-type diffusion layer are formed on the first collector layer 203A.
FIG. 2 is a graph showing the profile of a Ge percentage content (germanium percent content) and an impurity concentration with respect to a depth of the conventional SiGe base bipolar transistor. In the conventional SiGe base bipolar transistor, the first collector layer 203A having the first Ge concentration distribution and the second collector layer 203B having the second Ge concentration distribution (germanium concentration distribution) are formed in the N+-type buried layer 202 having the high concentration in which N-type impurity is doped at about 1020 cmxe2x88x923, as shown in FIG. 2. Then, the P-type SiGe base layer 210 in which P-type impurity is doped at about 5xc3x971018 cmxe2x88x923 and the poly-crystal silicon film 212 to pull out an emitter in which the N-type impurity is doped at about 2xc3x971020 cmxe2x88x923 are formed on the first collector layer 203A. The emitter layer 213 is formed by using the impurity thermal diffusion from the poly-crystal silicon film 212 to pull out an emitter in which the N-type impurity is doped.
With regard to the Ge concentration distribution of the P-type SiGe base layer 210, in the P-type SiGe base layer 210, an emitter region side has a low distribution, and a collector region side has a high distribution. That is, the emitter region side has a Ge percentage content of 0%, and the collector region side has a slant concentration distribution having a percentage content of 10%. FIG. 3 shows an energy band structure at this time.
FIG. 3 is a graph showing an energy band at the slant Ge profile (slant germanium profile). As shown in FIG. 3, in the case of the conventional SiGe base bipolar transistor, in the P-type crystal SiGe base layer 210, an inclination can be set for a conductive band side of an energy band, correspondingly to a Ge composition ratio (germanium composition ratio). Thus, an electron implanted from an emitter is accelerated in the P-type SiGe base layer 210 by an electrical field caused by the slant energy band structure. Hence, it is possible to reduce a base transit time of the electron and accordingly improve a cut-off frequency fT.
However, in the case of the conventional SiGe base bipolar transistor, in order to make the cut-off frequency fT higher by using the slant Ge profile, it is necessary to reduce a thickness of the P-type SiGe base layer 210. For example, it is noted that the thickness of the P-type SiGe base layer 210 is about 90 nm and the cut-off frequency fT=20 GHz. In order to set the cut-off frequency fT to 60 GHz, the thickness of the P-type SiGe base layer 210 must be reduced to about 30 nm. This brings about the following problems.
As the first problem, a constant region is narrow because of a drop in a current gain hFE in a high current region when the slant Ge profile is used, although an analog circuit especially requires that a current gain hFE (=collector current/base current) is constant in a wide current region of a collector current.
The reason is as follows. In the profile that the impurity concentration in the base is constant and the Ge concentration is slant such as the slant Ge profile, a collector current density Jc is represented by the following equation (1):                               J          ⁢                      xe2x80x83                    ⁢          c                =                                            q              ⁢                              xe2x80x83                            ⁢              D              ⁢                              xe2x80x83                            ⁢              n              ⁢                              xe2x80x83                            ⁢              n              ⁢                              xe2x80x83                            ⁢                              i                2                                                    NA              ⁢                              xe2x80x83                            ⁢              W              ⁢                              xe2x80x83                            ⁢              b                                ⁢                                    Δ              ⁢                              xe2x80x83                            ⁢              E              ⁢                              xe2x80x83                            ⁢              g              ⁢                              xe2x80x83                            ⁢              G              ⁢                              xe2x80x83                            ⁢                              e                ⁡                                  (                                      g                    ⁢                                          xe2x80x83                                        ⁢                    r                    ⁢                                          xe2x80x83                                        ⁢                    a                    ⁢                                          xe2x80x83                                        ⁢                    d                    ⁢                                          xe2x80x83                                        ⁢                    e                                    )                                                                    k              ⁢                              xe2x80x83                            ⁢              T                                ⁢                      exp            ⁡                          [                                                Δ                  ⁢                                      xe2x80x83                                    ⁢                  E                  ⁢                                      xe2x80x83                                    ⁢                  g                  ⁢                                      xe2x80x83                                    ⁢                  G                  ⁢                                      xe2x80x83                                    ⁢                                      e                    ⁡                                          (                      0                      )                                                                                        k                  ⁢                                      xe2x80x83                                    ⁢                  T                                            ]                                                          equation        ⁢                  xe2x80x83                ⁢                  (          1          )                    
xcex94EgGe(0): Contraction Amount of Band Gap by Ge at Tip of Depletion Layer between Emitter And Base
xcex94EgGe(grade): Ge Slant Amount in Neutral Base
Dn: Diffusion Constant of Electron in Base
NA: Base Impurity Concentration
Wb: Base Width
ni: Intrinsic Carrier Density
q: Charge
In the case of the slant Ge profile of the conventional SiGe base bipolar transistor, when the thickness of the P-type SiGe base layer 210 is reduced, this reduction causes the Ge inclinations (germanium inclinations) to be sharp at the positions of the formations of the emitter-base junction and the depletion layer between the emitter and the base. This results in a large reduction in a contraction amount xcex94Eg,Ge(0) of a band gap when the depletion layer between the emitter and the base is contracted as a voltage between the emitter and the base is made higher. Thus, the collector current is dropped in accordance with the equation (1), and the current gain hFE is largely dropped.
The second problem is the occurrence of a large variation in a collector current flowing when a certain voltage is applied between the base and the emitter. The variation in the collector current has great influence on a circuit operation when a transistor is used as a constant current source, for example, such as a case of an ECL circuit.
The reason of the variation in this collector current is as follows. The emitter layer 213 is formed by using the impurity thermal diffusion from the poly-crystal silicon film 212 to pull out an emitter in which the N-type impurity is doped. The reduction in the thickness of the P-type SiGe base layer 210 causes the Ge inclination (germanium inclination) to be sharp at the position where the emitter-base junction is formed. As a result, the slight variation at the junction position leads to the difference of the contraction amount xcex94Eg,Ge(0) in the band gap. That is, the collector current is proportional to the contraction amount xcex94Eg,Ge(0) in the band gap as an exponential function, which brings about the large variation in the collector current.
Japanese Laid Open Patent Application (JP-A-2000-31162) discloses the following hetero junction bipolar transistor. The hetero junction bipolar transistor is provided with: a collector layer constituted by a semiconductor containing a first conductive type impurity; a base layer that is provided adjacently to the collector layer and constituted by a compound crystal semiconductor containing a second conductive type impurity; and an emitter layer that is provided opposite to the collector layer with the base layer between and constituted by the semiconductor containing the first conductive type impurity. The base layer is provided such that a band gap of the compound semiconductor is gradually reduced from the emitter side towards the collector side and a concentration of the second conductive type impurity is gradually reduced from the emitter side towards the collector side.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-214399) discloses the following bipolar semiconductor device. The bipolar semiconductor device is provided with: a semiconductor layer having a first conductive type of a buried layer so as to form a collector region, on a substrate; a first insulation film formed on the semiconductor layer; a second conductive type of a first conductive film similarly formed on the semiconductor layer so as to form a base region, a second conductive type of a second conductive film which is formed on the first insulation film and connected to the first conductive film so as to form a base pull-out electrode; and a first conductive type of a third conductive film which is separated through a second insulation film from the second conductive film and formed on the first conductive film so as to form an emitter region, wherein the first insulation film and the second conductive film are coated with glass material insulation film, and the surface of the glass material insulation film is flat.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-79394) discloses the following bipolar transistor. The bipolar transistor at least contains: a first conductive type of a single crystal silicon layer; a many-layer film composed of a first insulation film having an opening provided on a surface of the first conductive type of the single crystal silicon layer, a second conductive type of a poly-crystal layer of a conductive type opposite to the first conductive type, and a second insulation film; a first conductive type of a single crystal silicon germanium layer provided in the opening; a second conductive type of a single crystal silicon germanium layer provided on the first conductive type of the single crystal silicon germanium layer; and a second conductive type of a poly-crystal silicon germanium layer placed in contact with both the second conductive type of the single crystal silicon germanium layer and the second conductive type of the poly-crystal layer.
Moreover, Japanese Publication Patent Application (JP-B2-Heisei, 07-44185) discloses the following semiconductor device. The semiconductor device is a bipolar transistor, in which on a silicon substrate or a silicon epitaxial layer having a first conductive type, has a compound crystal layer composed of silicon and germanium, and has a second conductive type impurity layer in the compound crystal, and has a silicon layer having a first conductive type impurity on the compound crystal layer of the silicon and the germanium, and has a hetero junction in a manner of forming a p-n junction on a boundary between the compound crystal layer of the silicon and the germanium and the silicon layer, wherein it is formed on the silicon substrate or the silicon epitaxial layer so that a germanium concentration included in the compound crystal composed of the silicon and the germanium is gradually higher towards the boundary between an outer compound crystal layer and the silicon layer thereon.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor device and a semiconductor manufacturing method, which can minimize a drop in a current gain at a time of an increase in a collector current density and also improve a variation in a collector current.
In order to achieve an aspect of the present invention, a semiconductor device, includes: a SiGe base bipolar transistor; and wherein the SiGe base bipolar transistor includes: an emitter layer; a collector layer; and a SiGe base layer formed of silicon containing germanium, and wherein a Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.
In this case, the SiGe base bipolar transistor includes: a P-type silicon substrate; and an N+-type buried layer having a high concentration formed in the P-type silicon substrate, and wherein the collector layer is formed of an N-type having a low concentration and is formed on the N+-type buried layer, and wherein the SiGe base bipolar transistor further including: an undoped SiGe layer in which an impurity is not doped, the undoped SiGe layer being formed on the N-type collector layer; a first SiGe base layer as a part of the SiGe base layer having a first Ge concentration distribution formed on the undoped SiGe layer; and a second SiGe base layer as another part of the SiGe base layer having a second Ge concentration distribution formed on the first SiGe base layer, and wherein the emitter layer is formed of an N-type diffusion layer formed in the second SiGe base layer.
In this case, an N-type impurity is doped at about 1016 cmxe2x88x923 as the low concentration of the N-type collector layer, and the N-type impurity is doped at about 1020 cmxe2x88x923 as the high concentration of the N+-type buried layer.
Also in this case, the undoped SiGe layer has a Ge concentration of about 10% and a thickness of about 30 nm.
Further in this case, a P-type impurity is doped at about 1xc3x971019 cmxe2x88x923 in the first SiGe base layer and the second SiGe base layer.
Further in this case, the semiconductor device further includes: a poly-crystal silicon film to pull out an emitter in which an N-type impurity is doped at about 2xc3x971020 cmxe2x88x923, the poly-crystal silicon film being formed on the second SiGe base layer.
In this case, the emitter layer is formed as a result that an impurity thermal diffusion is performed on the poly-crystal silicon film.
Also in this case, the SiGe base layer includes a first SiGe base layer and a second SiGe base layer, and wherein a thickness of the second SiGe base layer is about 20 nm, and a Ge concentration in the second SiGe base layer is increased from about 0% to about 2% from the side of the emitter layer towards the side of the collector layer, and wherein a thickness of the first SiGe base layer is about 10 nm, and a Ge concentration in the first SiGe base layer is increased from about 2% to about 10% from the side of the emitter layer towards the side of the collector layer.
Further in this case, the SiGe base bipolar transistor including: a P-type silicon substrate; and an N+-type buried layer having a high concentration in which an N-type impurity is doped at about 1020 cmxe2x88x923 formed in the P-type silicon substrate, and wherein the collector layer is formed of an N-type having a low concentration in which the N-type impurity is doped at about 1016 cmxe2x88x923 and is formed on the N+-type buried layer, and wherein the SiGe base bipolar transistor further including: an undoped SiGe layer in which an impurity is not doped, wherein the undoped SiGe layer is formed on the N-type collector layer and has a Ge concentration of about 10% and a thickness of about 30 nm; a third SiGe base layer as a part of the SiGe base layer having a third Ge concentration distribution formed on the undoped SiGe layer; a fourth SiGe base layer as another part of the SiGe base layer having a fourth Ge concentration distribution formed on the third SiGe base layer; and a Si base layer as other part of the SiGe base layer.
In this case, a P-type impurity is doped at about 1xc3x971019 cmxe2x88x923 in the third SiGe base layer, the fourth SiGe base layer and the Si base layer.
Also in this case, the semiconductor device further includes: a poly-crystal silicon film to pull out an emitter in which an N-type impurity is doped at about 2xc3x971020 cmxe2x88x923, the poly-crystal silicon film being formed on the Si base layer.
Further in this case, the emitter layer is formed as a result that an impurity thermal diffusion is performed on the poly-crystal silicon film.
In this case, the SiGe base layer includes a third SiGe base layer and a fourth SiGe base layer, and a Si base layer, and wherein a thickness of the Si base layer is about 20 nm, and wherein a thickness of the fourth SiGe base layer is about 5 nm, and a Ge concentration in the fourth SiGe base layer is increased from about 0% to about 2% from the side of the emitter layer towards the side of the collector layer, and wherein a thickness of the third SiGe base layer is about 5 nm, and a Ge concentration in the third SiGe base layer is increased from about 2% to about 10% from the side of the emitter layer towards the side of the collector layer.
In order to achieve another aspect of the present invention, a semiconductor with a SiGe base bipolar transistor manufacturing method, includes: (a) providing an emitter layer; (b) providing a collector layer; and (c) providing a SiGe base layer formed of silicon containing germanium, and wherein a Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.
Also in this case, the semiconductor with a SiGe base bipolar transistor manufacturing method further includes: (d) providing a P-type silicon substrate; and (e) forming an N+-type buried layer having a high concentration in the P-type silicon substrate, and wherein the collector layer is formed of an N-type having a low concentration and is formed on the N+-type buried layer, and wherein the semiconductor with the SiGe base bipolar transistor manufacturing method further including: (f) forming an undoped SiGe layer in which an impurity is not doped on the N-type collector layer; (g) forming a first SiGe base layer as a part of the SiGe base layer having a first Ge concentration distribution on the undoped SiGe layer; and (h) forming a second SiGe base layer as another part of the SiGe base layer having a second Ge concentration distribution on the first SiGe base layer, and wherein the emitter layer is formed of an N-type diffusion layer formed in the second SiGe base layer.
In this case, an N-type impurity is doped at about 1016 cmxe2x88x923 as the low concentration of the N-type collector layer, and the N-type impurity is doped at about 1020 cmxe2x88x923 as the high concentration of the N+-type buried layer.
Also in this case, the undoped SiGe layer has a Ge concentration of about 10% and a thickness of about 30 nm.
Further in this case, a P-type impurity is doped at about 1xc3x971019 cmxe2x88x923 in the first SiGe base layer and the second SiGe base layer.
In this case, the semiconductor with a SiGe base bipolar transistor manufacturing method further includes: (i) forming a poly-crystal silicon film to pull out an emitter in which an N-type impurity is doped at about 2xc3x971020 cmxe2x88x923 on the second SiGe base layer.
Also in this case, the emitter layer is formed as a result that an impurity thermal diffusion is performed on the poly-crystal silicon film.
Further in this case, the SiGe base layer includes a first SiGe base layer and a second SiGe base layer, and wherein a thickness of the second SiGe base layer is about 20 nm, and a Ge concentration in the second SiGe base layer is increased from about 0% to about 2% from the side of the emitter layer towards the side of the collector layer, and wherein a thickness of the first SiGe base layer is about 10 nm, and a Ge concentration in the first SiGe base layer is increased from about 2% to about 10% from the side of the emitter layer towards the side of the collector layer.
In this case, the semiconductor with a SiGe base bipolar transistor manufacturing method further includes: (j) providing a P-type silicon substrate; and (k) forming an N+-type buried layer having a high concentration in which an N-type impurity is doped at about 1020 cmxe2x88x923 in the P-type silicon substrate, and wherein the collector layer is formed of an N-type having a low concentration in which the N-type impurity is doped at about 1016 cmxe2x88x923 and is formed on the N+-type buried layer, and wherein the semiconductor with the SiGe base bipolar transistor manufacturing method further including: (I) forming an undoped SiGe layer in which an impurity is not doped on the N-type collector layer, the undoped SiGe layer having a Ge concentration of about 10% and a thickness of about 30 nm; (m) forming a third SiGe base layer as a part of the SiGe base layer having a third Ge concentration distribution on the undoped SiGe layer; (n) forming a fourth SiGe base layer as another part of the SiGe base layer having a fourth Ge concentration distribution on the third SiGe base layer; and (o) forming a Si base layer as other part of the SiGe base layer.
Also in this case, a P-type impurity is doped at about 1xc3x971019 cmxe2x88x923 in the third SiGe base layer, the fourth SiGe base layer and the Si base layer.
Further in this case, the semiconductor with a SiGe base bipolar transistor manufacturing method, further includes: (p) forming a poly-crystal silicon film to pull out an emitter in which an N-type impurity is doped at about 2xc3x971020 cmxe2x88x923 on the Si base layer.
In this case, the emitter layer is formed as a result that an impurity thermal diffusion is performed on the poly-crystal silicon film.
Also in this case, the SiGe base layer includes a third SiGe base layer and a fourth SiGe base layer, and a Si base layer, and wherein a thickness of the Si base layer is about 20 nm, and wherein a thickness of the fourth SiGe base layer is about 5 nm, and a Ge concentration in the fourth SiGe base layer is increased from about 0% to about 2% from the side of the emitter layer towards the side of the collector layer, and wherein a thickness of the third SiGe base layer is about 5 nm, and a Ge concentration in the third SiGe base layer is increased from about 2% to about 10% from the side of the emitter layer towards the side of the collector layer.
The purpose of the present invention characteristically lies in a semiconductor device containing a SiGe base bipolar transistor having a slant Ge profile in which a Ge concentration of a SiGe base layer is increased from 0% to 10% from an emitter region side towards a collector region side.
In this case, an N+-type buried layer having a high concentration and an N-type collector layer having a low concentration are formed on a P-type silicon substrate of the SiGe base bipolar transistor, and an undoped SiGe layer in which an impurity is not doped, a first SiGe base layer having a first Ge concentration distribution and a second SiGe base layer having a second Ge concentration distribution are formed on the N-type collector layer having the low concentration, and an emitter layer made of an N-type diffusion layer is formed on the second SiGe base layer.
Also in this case, the SiGe base bipolar transistor is formed such that the N-type collector layer having the low concentration in which an N-type impurity is doped at about 1016 cmxe2x88x923 is formed on the N+-type buried layer having the high concentration in which the N-type impurity is doped at about 1020 cmxe2x88x923.
Further in this case, the SiGe base bipolar transistor is formed such that the undoped SiGe layer having a Ge concentration of about 10% and a thickness of about 30 nm, the first SiGe base layer having a first Ge concentration distribution and the second SiGe base layer having a second Ge concentration distribution are formed on the N-type collector layer having the low concentration.
In this case, the SiGe base bipolar transistor is formed such that the P-type impurity is doped at about 1xc3x971019 cmxe2x88x923in the first SiGe base layer and the second SiGe base layer.
Also in this case, the SiGe base bipolar transistor is formed such that a poly-crystal silicon film to pull out an emitter in which the N-type impurity is doped at about 2xc3x971020 cmxe2x88x923 is formed on the second SiGe base layer.
Further in this case, the emitter layer of the SiGe base bipolar transistor is formed by using the impurity thermal diffusion from the poly-crystal silicon film to pull out the emitter in which the N-type impurity is doped.
In this case, the SiGe base bipolar transistor is designed such that a thickness of the second SiGe base layer is about 20 nm, a Ge concentration is increased from about 0% to about 2% from the emitter region side towards the collector region side in the second SiGe base layer, a thickness of the first SiGe base layer is about 10 nm, and a Ge concentration in the first SiGe base layer is increased from about 2% to about 10%.
Also in this case, the SiGe base bipolar transistor is formed such that the N-type collector layer of the low concentration in which the N-type impurity is doped at about 1016 cmxe2x88x923 on the N+-type buried layer having the high concentration in which the N-type impurity is doped at about 1020 cmxe2x88x923, and the undoped SiGe layer having a Ge concentration of about 10% and a thickness of about 30 nm, a third SiGe base layer having a third Ge concentration distribution, a fourth SiGe base layer having a fourth Ge concentration distribution, and a Si base layer are formed on the N-type collector layer having the low concentration.
Further in this case, the SiGe base bipolar transistor is formed by the formation of a poly-crystal silicon film to pull out an emitter, in which the P-type impurity is doped at about 1xc3x971019 cmxe2x88x923 on the third SiGe base layer, the fourth SiGe base layer and the Si base layer, and the N-type impurity is doped at about 2xc3x971020 cmxe2x88x923 on the Si base layer.
In this case, the emitter layer of the SiGe base bipolar transistor is formed by using the impurity thermal diffusion from the poly-crystal silicon film to pull out the emitter in which the N-type impurity is doped.
Also in this case, the SiGe base bipolar transistor is designed such that a thickness of the Si base layer is about 20 nm, a thickness of the fourth SiGe base layer is about 5 nm, a Ge concentration is increased from about 0% to about 2% from the emitter region side in the fourth SiGe base layer, a thickness of the third SiGe base layer is about 5 nm, and a Ge concentration in the third SiGe base layer is increased from about 2% to about 10%.
The semiconductor manufacturing method has a step of forming a SiGe base bipolar transistor having a slant Ge profile in which a Ge concentration of a SiGe base layer is increased from 0% to 10% from an emitter region side towards a collector region side.
In this case, the present invention further includes the steps of: forming the N-type collector layer having the low concentration in which the N-type impurity is doped at about 1016 cmxe2x88x923, on the N+-type buried layer having the high concentration in which the N-type impurity is doped at about 1020 cmxe2x88x923; forming the undoped SiGe layer having a Ge concentration of about 10% and a thickness of about 30 nm, the first SiGe base layer having a first Ge concentration distribution, and the second SiGe base layer having a second Ge concentration distribution, on the N-type collector layer having the low concentration; doping the P-type impurity at about 1xc3x971019 cmxe2x88x923 on the first SiGe base layer and the second SiGe base layer; forming a poly-crystal silicon film to pull out an emitter in which the N-type impurity is doped at 2xc3x971020 cmxe2x88x923, on the second SiGe base layer; and setting a thickness of the second SiGe base layer to about 20 nm, increasing the Ge concentration from about 0% to about 2% from an emitter region side towards a collector region side in the second SiGe base layer, setting a thickness of the first SiGe base layer to about 10 nm, and increasing the Ge concentration in the first SiGe base layer from about 2% to about 10%.
The semiconductor manufacturing method further includes the steps of: forming the N-type collector layer having the low concentration in which the N-type impurity is doped at about 1016 cmxe2x88x923, on the N+-type buried layer having the high concentration in which the N-type impurity is doped at about 1020 cmxe2x88x923; forming the undoped SiGe layer having a Ge concentration of about 10% and a thickness of about 30 nm, a third SiGe base layer having a third Ge concentration distribution, a fourth SiGe base layer having a fourth Ge concentration distribution and a Si base layer, on the N-type collector layer having the low concentration; doping the P-type impurity at about 1xc3x971019 cmxe2x88x923 on the third SiGe base layer, the fourth SiGe base layer and the Si base layer; forming a poly-crystal silicon film to pull out an emitter in which the N-type impurity is doped at 2xc3x971020 cmxe2x88x923, on the Si base layer; forming an emitter layer by using the impurity thermal diffusion from the poly-crystal silicon film to pull out the emitter in which the N-type impurity is doped; and setting a thickness of the Si base layer to about 20 nm, setting a thickness of the fourth SiGe base layer to about 5 nm, increasing the Ge concentration from about 0% to about 2% from an emitter region side in the fourth SiGe base layer, and also setting a thickness of the third SiGe base layer to about 5 nm, and then increasing the Ge concentration in the third SiGe base layer from about 2% to about 10%.